difference between "Coverage summary by istance" and "Design Unit Coverage Details"

Question

In an FPGA project what is the difference between:

1. Coverage summary by istance
2. Local Istance Coverage Details
3. Recursive Hierarchical Coverage Details
4. Design Unit Coverage Details

Answer 1

These are mainly hardware verification terminologies. And also to some extent simulation tool specific terminologies. StackOverflow post about Testing FPGA Designs at Different Levels is may be helpful for you.

In FPGA development there are some mission critical sectors where you need a maximum functional coverage (functional verification of every requirement) and code coverage like statement, branch, expression, conditions etc. Hence you lay out coverage plans.

For instance, Advanced FPGA Design Architecture, Implementation, and Optimization mentions about FPGA based coverage as follows:

Due to the ability of an FPGA to rapidly prototype the design and to run vectors real-time in hardware, the development time for gate-level code coverage is rarely justified. That said, code coverage can still be useful at the gate level as it is at the RTL level. When running a gate-level simulation, the code coverage analysis will provide a coverage number relative not to the logical constructs but to the physical elements themselves.

Having said that, you will find explicit differences about these terminologies at Forums: Coverage of Verification Academy. For example, in this forum you will find Different coverage report for different covergroup instance