Addition with 7-Segment Display

Question

I am trying to add the 2 outputs together and show their result in a third/fourth display on the 7 segment display. Each output is shown in their own segment respectively. The fourth display being a double digit number (Max being 14, Min being 0). I am getting an error stating that I need to write all instances of the case "add". Not sure where to go from here. Any help is appreciated.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  Midterm2_Q2_4369 IS
PORT (

SW: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SW0: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

ADD: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y0: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y1: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

Y2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END Midterm2_Q2_4369;
ARCHITECTURE MUX8 OF Midterm2_Q2_4369 IS 
BEGIN
PROCESS (SW,SW0,ADD)
BEGIN
CASE SW IS
WHEN "000" => Y <= "0000001";

WHEN "001" => Y <= "1001111";

WHEN "010" => Y <= "0010010";

WHEN "011" => Y <= "0000110";

WHEN "100" => Y <= "1001100";

WHEN "101" => Y <= "0100100";

WHEN "110" => Y <= "0100000";

WHEN "111" => Y <= "0001111";
END CASE;

CASE SW0 IS
WHEN "000" => Y0 <= "0000001";

WHEN "001" => Y0 <= "1001111";

WHEN "010" => Y0 <= "0010010";

WHEN "011" => Y0 <= "0000110";

WHEN "100" => Y0 <= "1001100";

WHEN "101" => Y0 <= "0100100";

WHEN "110" => Y0 <= "0100000";

WHEN "111" => Y0 <= "0001111";
END CASE;

CASE ADD IS
WHEN "0000000" => Y1 <= "0000001"; --0

WHEN "0000001" => Y1 <= "1001111"; --1

WHEN "0000010" => Y1 <= "0010010"; --2

WHEN "0000011" => Y1 <= "0000110"; --3

WHEN "0000100" => Y1 <= "1001100"; --4

WHEN "0000101" => Y1 <= "0100100"; --5

WHEN "0000110" => Y1 <= "0100000"; --6

WHEN "0000111" => Y1 <= "0001111"; --7

WHEN "0001111" => Y1 <= "0000000"; --8

WHEN "0010111" => Y1 <= "0000100"; --9
     --8421421
WHEN "0011111" => Y2 <= "1001111"; --(1)0

WHEN "0100111" => Y2 <= "1001111"; --(1)1

WHEN "0101111" => Y2 <= "1001111"; --(1)2

WHEN "0110111" => Y2 <= "1001111"; --(1)3

WHEN "0111111" => Y2 <= "1001111"; --(1)4--

WHEN "1000111" => Y2 <= "1001111"; --(1)5

WHEN "1001111" => Y2 <= "1001111"; --(1)6

WHEN "1010111" => Y2 <= "1001111"; --(1)7--

WHEN "1011111" => Y2 <= "1001111"; --(1)8

WHEN "1100111" => Y2 <= "1001111"; --(1)9
END CASE;

END PROCESS;
END MUX8;

Answer 1

When using a case in VHDL, all cases MUST be covered. Becasue SW, SW0 and ADD are all std_logic_vector, you must also cover all of the meta cases like "UUUUUUUU", etc. The easiest way to do this is with others.

For example. SW0 has all "real" cases covered, but you must also cover values that can only occur in simulation, so provide a handy message:

CASE SW0 IS
  WHEN "000" => Y0 <= "0000001";
  WHEN "001" => Y0 <= "1001111";
  WHEN "010" => Y0 <= "0010010";
  WHEN "011" => Y0 <= "0000110";
  WHEN "100" => Y0 <= "1001100";
  WHEN "101" => Y0 <= "0100100";
  WHEN "110" => Y0 <= "0100000";
  WHEN "111" => Y0 <= "0001111";
  when others => report "Meta value detected" severity warning;-- simulation only case
END CASE;

You must also ensure all cases are covered for SW and ADD too