Output not as expected when implementing 4-bit SISO register in VHDL

Question

I am trying to create a 4-bit SISO register in VHDL, and this is my main code:

library ieee;
use ieee.std_logic_1164.all;

entity right_shift_siso_reg_4 is
port(
    D_in  : in std_logic;
    clk   : in std_logic;
    D_out : out std_logic
);
end right_shift_siso_reg_4;

architecture structural of right_shift_siso_reg_4 is
    signal Q0, Q1, Q2: std_logic;
    component d_flip_flop is
        port(
            D   : in std_logic;
            clk : in std_logic;
            Q   : out std_logic;
            Q_bar : out std_logic
        );
    end component;
begin
    dff0: d_flip_flop port map(D=>D_in, clk=>clk, Q=>Q0);
    dff1: d_flip_flop port map(D=>Q0, clk=>clk, Q=>Q1);
    dff2: d_flip_flop port map(D=>Q1, clk=>clk, Q=>Q2);
    dff3: d_flip_flop port map(D=>Q2, clk=>clk, Q=>D_out);
end structural; 

And this is the code for the component d_flip_flop that above program uses:

library ieee;
use ieee.std_logic_1164.all;

entity d_flip_flop is
port(
    D     : in std_logic;
     clk   : in std_logic;
     Q     : out std_logic;
     Q_bar : out std_logic
);
end d_flip_flop;

architecture behavioral of d_flip_flop is
begin
    process(clk, D)
     begin
         if(clk'event and clk = '1') then
              Q <= D; --at rising clk. pulse if D=1, Q=1 & if D=0, Q=0
              Q_bar <= NOT D;
          end if;
     end process;    
end behavioral;

The code runs, but the output simulation that I've received seems to have problems.

As far as I know, the output signal received should be same as the input signal except it comes out shifted (probably by T=3 in this case). But if you look at the result here that is not the case (the 1st high input runs for T= 5units, but the 1st high output runs for T = 6units).

What is the problem here?

Answer 1

Your design doesn't look like having any problem. I wrote a testbench and tried it out myself. Here is the testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity testbench is
--  Port ( );
end testbench;

architecture Behavioral of testbench is
    component right_shift_siso_reg_4 is
    port(
        D_in  : in std_logic;
        clk   : in std_logic;
        D_out : out std_logic
    );
    end component;
    
    signal clk, test_din, test_dout : std_logic;
    
begin
    UUT: right_shift_siso_reg_4 port map(D_in=>test_din, clk=>clk, D_out=>test_dout);
    
    -- Clock Process
    process begin
        clk <= '0';
        wait for 5ns;
        
        clk <= '1';
        wait for 5ns;
    end process;
    
    -- Test Scenario
    process begin
        test_din <= '0';
        wait for 15ns;
        
        test_din <= '1';
        wait for 10ns;
        
        test_din <= '0';
        wait;
    end process;

end Behavioral;

The output is the same as yours. If you look at the output of each DFF module, you will see that the first one doesn't work properly. It assigns the input to the output directly.

However, when I tried to create another signal at the top module and assigned the D_in to it first, the problem is solved. Check out the little modification on the code below.

library ieee;
use ieee.std_logic_1164.all;

entity right_shift_siso_reg_4 is
port(
    D_in  : in std_logic;
    clk   : in std_logic;
    D_out : out std_logic
);
end right_shift_siso_reg_4;

architecture structural of right_shift_siso_reg_4 is
    signal Q0, Q1, Q2: std_logic;
    signal dummy : std_logic;
    component d_flip_flop is
        port(
            D   : in std_logic;
            clk : in std_logic;
            Q   : out std_logic;
            Q_bar : out std_logic
        );
    end component;
begin
    dummy <= D_in;

    dff0: d_flip_flop port map(D=>dummy, clk=>clk, Q=>Q0);
    dff1: d_flip_flop port map(D=>Q0, clk=>clk, Q=>Q1);
    dff2: d_flip_flop port map(D=>Q1, clk=>clk, Q=>Q2);
    dff3: d_flip_flop port map(D=>Q2, clk=>clk, Q=>D_out);
end structural; 

The waveforms of the test result are as below. It's been a long time since I work on digital design. That's all from me, try to advance yourself, my friend :)

Answer 2

The output you've shown is correct.

if(clk'event and clk = '1')

This line looks for positive edges of clk, not just edges. If you look at your output carefully, D_in is sampled at positive edge 60.0ns and come out at 40*3 + 60 = 180ns

I think you calculated using both edges of clock and not positive edges.