I've been studying Pedroni's Circuit Design and Simulation in VHDL from 2010. I have an Open3S500E development board and am using Xilinx ISE 14.7 (newer don't support Spartan 3). I have been stuck on "Exercise 9.5: Function my_not" which requires to use a resolution table(?):
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CONSTANT not_table: stdlogic_1d :=
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-- U X 0 1 Z W L H -
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( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
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regardless of what I did I always received an Error Unsupported type stdlogic_1d . I tried different things but failed every time. Finally I decided to copy and build Example 9.6 which used a similar table:
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_ULOGIC;
CONSTANT and_table: stdlogic_table := (
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--U X 0 1 Z W L H -
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( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), --| U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), --| 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --| 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), --| L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --| H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); --| - |
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..and I got the same result. Finally, I came to conclusion that there must be something wrong with Spartan 3 and changed family to Spartan 6 which worked like a charm.
There are couple of questions on my mind here. Why does it work on Spartan 6 and on Spartan 3? Must be about indexing with STD_LOGIC, right? I thought this was language specific feature and not hardware related. Are STD_LOGIC values enumerated somewhere? If so, what difference does it make if I index with 'U' or 0?. I know it's kind of a specific question and in the end it doesn't matter since Spartan 3 is already ancient, but I would love to know the answer.
Disclaimer: I am a VHDL newbie and an amateur programmer.
---------Package:-----------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------------------------
PACKAGE PEX9_6 IS
FUNCTION my_and (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
END PACKAGE;
----------------------------------------------------------------------
PACKAGE BODY PEX9_6 IS
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_ULOGIC;
CONSTANT and_table: stdlogic_table := (
-----------------------------------------------
--UX01ZWLH-
-----------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), --| U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), --| 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --| 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --| W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), --| L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --| H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); --| - |
-----------------------------------------------
FUNCTION my_and (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
ALIAS aa: STD_LOGIC_VECTOR(1 TO a'LENGTH) IS a;
ALIAS bb: STD_LOGIC_VECTOR(1 TO b'LENGTH) IS b;
VARIABLE result: STD_LOGIC_VECTOR(1 TO a'LENGTH);
BEGIN
FOR i IN result'RANGE LOOP
result(i) := and_table (aa(i), bb(i));
END LOOP;
RETURN result;
END FUNCTION;
END PACKAGE BODY;
Main code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library functions_and_procedures;
USE functions_and_procedures.PEX9_6.all;
-------------------------------------------------
ENTITY EX9_6 IS
PORT (x1, x2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
-------------------------------------------------
ARCHITECTURE myand OF EX9_6 IS
BEGIN
y <= my_and(x1, x2);
END ARCHITECTURE;
-------------------------------------------------
Error message: ERROR:Xst:2092 - "D:/FPGA/Projects/Pedroni2010/PEX9_6.vhd" line 40: Unsupported type stdlogic_table.