My processor is an STM32F746ZGT6 and I wish to use TCD132DG, so I need to generate two synchronous clock pulses with different frequencies (One of them is 2 MHz and the other one is 500 KHz) so I used two different timers in output compare mode. The problem is that these two pulses have phase shift. In the Datasheet of TCD132DG the maximum allowed time shift is 60ns while the pulses have 240ns time shift.
Thanks, Amir Reza
Set up the timers in a master-slave configuration so that enabling one timer starts the other. For example,
TIM1master mode to send its Enable as trigger output (MMS=001in theTIM3->CR2register).TIM2to get the input trigger fromTIM1(TS=000in theTIM2->SMCRregister).TIM2in trigger mode (SMS=110in theTIM2->SMCRregister).CENbit ofTIM1->CR1should start both timers at once.