V_SUB_F64 in AMD's GCN and VEGA instruction set

Question

Why there is no V_SUB_F64 instruction in AMD's GCN and VEGA instruction set? How do they realize the double precision subtraction?

Answer 1

In section 6.2.1, "Instruction Inputs" of the Instruction Set Architecture document it says:

Instructions using the VOP3 form and also using floating-point inputs have the option of applying absolute value (ABS field) or negate (NEG field) to any of the input operands.

V_ADD_F64 is listed as a VOP3-encoded instruction, so you can negate either or both of the operands to produce (a + b), (a - b), (-a + b), or (-a - b).