The explanation below is taken from the boom's documentation.
all other exceptions and interrupts can be handled before the instruction is dispatched to the ROB
I understand the interrupts are taken at the decode stage. I assume it is placed at ROB and fires when it comes to the head of ROB (I assume in this way because CSRs are not renamed so it cannot be executed speculatively). In this way, an interrupt might fire too late according to the size of ROB and the fullness of ROB. Isn't it a problem? What should be the correct implementation when we think of out-of-order architecture with up to hundreds of instructions in the pipe after decode stage?