How to connect combo code to a module's interface modport?

Question

Inside my top level SystemVerilog module is an instance, (rd_blk), that has an interface modport, (sec_rd). I need to temporarily connect it to combinational code, but I'm having difficulty coming up with an error free solution. Suggestions please.

interface sec_rd_if (
  input wire clk
);

logic       sec_rd;
logic [7:0] sec_rd_addr;
logic       sec_rd_rdy;

modport dst (
  input  sec_rd,
  input  sec_rd_addr,
  output sec_rd_rdy,
);

modport src (
  output sec_rd,
  output sec_rd_addr,
  input  sec_rd_rdy,
);

endinterface


module dst_rd_blk (
  input logic    clk,
  sec_rd_if.dst  sec_rd
);
  < main rtl code >
endmodule


module top (
  input logic clk
);

  always_comb begin
  // Combo logic to connect to sec_rd port goes here?
  end

  dst_rd_blk rd_blk (
    .clk (clk),
    .sec_rd (???)
  );

endmodule

Answer 1

Your code is missing an instance of the interface. I added one in top:

module dst_rd_blk (
  input logic    clk,
  sec_rd_if.dst  sec_rd
);
  //< main rtl code >
endmodule


module top (
  input logic clk
);

  always_comb begin
  // Combo logic to connect to sec_rd port goes here?
  end

sec_rd_if sec_rd_if (.clk(clk));

dst_rd_blk rd_blk (
    .clk (clk),
    .sec_rd (sec_rd_if)
  );

endmodule

The code compiles without errors.

Answer 2

You cannot leave an interface port unconnected. You cannot make selective connections the signals inside an interface.

However, you can make assignments to selective variables directly inside the interface from your testbench.

module top (
  input logic clk
);

  logic sec_rd;
  always_comb begin
     if_inst.sec_rd = 0;
  end
   
  
  sec_rd_if if_inst(clk);

  dst_rd_blk rd_blk (
    .clk (clk),
    .sec_rd(if_inst.dst)
  );

endmodule

If you need to overwrite something else that is making assignments to that signal, you can use a force statement.