Logical Error in Verilog code for converting SR FF to JK FF

Question

I have created a default design of SR FF and using module instantiation I am trying to create a JK FF from SR FF module.I am not facing any syntax error but all my outputs are comming to be 0 in all the condiitons of J and K values as I have taken datatype of q to be bit.Here is the code.

Here is the code.

// Design Code
module JK_FF(output reg q, input j,k,clk);

    reg qbar;
    wire qjk;
    wire s=0,r=0;
    assign qjk = q;
    SR_FF sr(s,r,clk,q,qbar);  
    assign s=j&~qjk;
    assign r=k&qjk;

endmodule

module SR_FF(input s,r,clk, output reg q, qbar);

    always@(posedge clk)
      begin 
        if(s == 1)
          begin
            q = 1;
            qbar = 0;
          end
         else if(r == 1)
          begin
            q = 0;
            qbar =1;
          end   
         else if(s == 0 & r == 0) 
          begin 
            q <= q;
            qbar <= qbar;
          end
      end

endmodule

// Testbench Code
<pre></code>
module JK_TB;
bit j,k, clk;
bit q;

    JK_FF dut(.q(q), .j(j), .k(k), .clk(clk)); 
    
    always #5 clk = ~clk;  
    
    initial 
      clk <= 0;
    
    initial begin 
      j = 0; k = 1;
      #10; j = 1; k = 0; 
      #10; j = 0; k = 0; 
      #10; j = 1; k = 1; 
      #10; j = 0; k = 1; 
      #10; j = 0; k = 0; 
    end 
    
    initial begin
      $monitor($time, "\t clk = %b j = %b k = %b q = %b",clk,j,k,q);
      #60 $finish;
    end

endmodule
</pre></code>

//Output

Parsing design file 'design.sv'
Parsing design file 'testbench.sv'
Top Level Modules:
JK_TB
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...

1 module and 0 UDP read.
recompiling module JK_TB

rm -f _cuarc\*.so csrc\*.so pre_vcsobj_\*.so share_vcsobj\*.so
if \[ -x ../simv \]; then chmod a-x ../simv; fi
g++  -o ../simv      -m32 -m32 -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/apps/vcsmx/vcs/S-2021.09/linux/lib -L/apps/vcsmx/vcs/S-2021.09/linux/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed   objs/amcQw_d.o   \_322_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o           -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /apps/vcsmx/vcs/S-2021.09/linux/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive          /apps/vcsmx/vcs/S-2021.09/linux/lib/vcs_save_restore_new.o /apps/vcsmx/vcs/S-2021.09/linux/lib/ctype-stubs_32.a -ldl  -lc -lm -lpthread -ldl
../simv up to date
CPU time: .215 seconds to compile + .404 seconds to elab + .220 seconds to link
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09;  Mar 18 14:44 2024
0    clk = 0 j = 0 k = 1 q = 0
5    clk = 1 j = 0 k = 1 q = 0
10   clk = 0 j = 1 k = 0 q = 0
15   clk = 1 j = 1 k = 0 q = 0
20   clk = 0 j = 0 k = 0 q = 0
25   clk = 1 j = 0 k = 0 q = 0
30   clk = 0 j = 1 k = 1 q = 0
35   clk = 1 j = 1 k = 1 q = 0
40   clk = 0 j = 0 k = 1 q = 0
45   clk = 1 j = 0 k = 1 q = 0
50   clk = 0 j = 0 k = 0 q = 0
55   clk = 1 j = 0 k = 0 q = 0
$finish called from file "testbench.sv", line 28.
$finish at simulation time                   60
V C S   S i m u l a t i o n   R e p o r t
Time: 60 ns
CPU Time:      0.540 seconds;       Data structure size:   0.0Mb
Mon Mar 18 14:44:47 2024