Modify verilog mode indentation

Question

I am trying to have verilog mode indent everything using 2 spaces except decls and always. This is what I added to my .emacs:

;; `define are not indented                                                                                                                                                                                                                                                    
(setq       verilog-indent-level-directive 0)
;;  always, initial etc not indented                                                                                                                                                                                                                                           
(setq       verilog-indent-level-module    0)
;; logic declarations are not indented                                                                                                                                                                                                                                         
(setq       verilog-indent-level-declaration 0)
;;2 space indent                                                                                                                                                                                                                                                               
(setq       verilog-indent-level             2)
;; no indent on list and no indent when on multiple lines                                                                                                                                                                                                                      
(setq       verilog-indent-lists           nil)
(setq       verilog-cexp-indent              0)

These is the result on a test module

`ifndef MY_MODULE_SV
`define MY_MODULE_SV

module my_module #(                                                                                                                                                                                                                                                            
parameter MyPar1 = 16,                                                                                                                                                                                                                                                         
parameter MyPar2 = 32                                                                                                                                                                                                                                                          
                   ) (
                   input logic        clk,
                   input logic        reset,
//comment indented weirdly                                                                                                                                                                                                                                                               
                   output logic [3:0] result
                   );

logic [3:0]                           count;


always @(posedge clk) begin
  //comment indented ok
  if (reset) begin
    count  <= 0;
    result <= 0;
  end
  else begin
    result   <= count;
    count    <= count+1;
  end
end

endmodule; // my_module                                                                                                                                                                                                                                                        

`endif

The part that is not correct are the port and parameter list. Also the declaration of count gets aligned to the port declarations, which is strange. I would like this to look like:

module my_module #(                                                                                                                                                                                                                                                            
  parameter MyPar1 = 16,                                                                                                                                                                                                                                                         
  parameter MyPar2 = 32                                                                                                                                                                                                                                                          
) (
  input logic        clk,
  input logic        reset,
  //result signal                                                                                                                                                                                                                                                                
  output logic [3:0] result
);

I am using emacs 24.3.1 I am not sure how to tweak this using only the variables provided by the verilog mode, any suggestion?

Answer 1

Recent versions of verilog-mode have the verilog-indent-lists option which when set to nil results in the desired behavior:

(setq verilog-indent-lists nil)

Answer 2

This doesn't exactly match your requested layout, but what I do is put the #( below the module keyword and split the end paren from the parameter list and the begin paren for the port list onto separate lines. The result is below. All of my indentation is for 3 spaces, but you could tweak that to suit your needs:

module my_module 
   #(
     parameter MyPar1 = 16,
     parameter MyPar2 = 32
     )
   (
    input logic        clk,
    input logic        reset,
    //comment indented weirdly
    output logic [3:0] result
    );

   logic [3:0]         count;

   always @(posedge clk) begin
      //comment indented ok
      if (reset) begin
         count  <= 0;
         result <= 0;
      end
      else begin
         result   <= count;
         count    <= count+1;
      end
   end

endmodule; // my_module                                                                                                                                                                                                                                                        

The verilog mode related section of my .emacs file is below:

(custom-set-variables
 '(verilog-align-ifelse t)
 '(verilog-auto-delete-trailing-whitespace t)
 '(verilog-auto-inst-param-value t)
 '(verilog-auto-inst-vector nil)
 '(verilog-auto-lineup (quote all))
 '(verilog-auto-newline nil)
 '(verilog-auto-save-policy nil)
 '(verilog-auto-template-warn-unused t)
 '(verilog-case-indent 3)
 '(verilog-cexp-indent 3)
 '(verilog-highlight-grouping-keywords t)
 '(verilog-highlight-modules t)
 '(verilog-indent-level 3)
 '(verilog-indent-level-behavioral 3)
 '(verilog-indent-level-declaration 3)
 '(verilog-indent-level-module 3)
 '(verilog-tab-to-comment t))