System Verilog parameterize Module Name

Question

Assuming in the design, all module's input/output ports are the same. however, the module name are different and number of module counts are different by project.

Is it possible to have 2 parameters -> Can it be synthesiable ?

   parameter NUM_OF_MODULE_COUNTS = 10,
   parameter string MODULE_NAME[10] = {module_a,module_b,.....} 

genvar i ;

generate
 for (i==0;i<NUM_OF_MODULE_COUNTS; i++)
    MODULE_NAME[i] u_inst (.port_a(a), .port_b(b)).....);
endgenerate

Answer 1

There is no way to use strings as identifier names in SystemVerilog.

The only feature that comes remotely close to what you want to do is a configuration config where you can map each instance of an array of instantiated modules to a module of the same name but from different libraries.

module top;
for (genvar i==0;i<NUM_OF_MODULE_COUNTS; i++) begin : block
    MOD u_inst (.port_a(a), .port_b(b)).....);
end
endmodule

And then in your config file you would have

instance top.block[0].u_inst use lib0;
instance top.block[1].u_inst use lib1;
instance top.block[2].u_inst use lib2;

And then you would need to compile the different versions of MOD into each library.

But in the end, it might just be simpler to type

    module_a u_insta (.port_a(a), .port_b(b)).....);
    module_b u_instb (.port_a(a), .port_b(b)).....);
    module_c u_instc (.port_a(a), .port_b(b)).....);